Principal Static Timing Analysis (STA) Engineer – SoC Design
with advanced timing concepts: SI, CDC, LVF, POCV, etc. Proficiency in STA tools (e.g., Synopsys PrimeTime), scripting, and UNIX...
with advanced timing concepts: SI, CDC, LVF, POCV, etc. Proficiency in STA tools (e.g., Synopsys PrimeTime), scripting, and UNIX...
with EDA tools such as Synopsys Fusion Compiler, Synopsys RTL-Architect, PrimePower,PrimeTime and Prime Closure Script writing...
and experience, typically from 3 years to 20 years. · Experience with Verilog/SystemVerilog design, Synopsys synthesis, low power...
Spectre Synopsys PrimeSim AFS or equivalent Solid understanding of analog/mixed-signal design flows, including...
design and verification (e.g., Cadence, Synopsys). Experience with lab equipment for signal integrity analysis and debugging...
components for Qualcomm's SoCs. Uses HDL languages (Verilog, SystemVerilog), know-how of front-end simulation tools (Synopsys... Verdi), power analysis tools (Synopsys PTPX, synthesis tools like Synopsys Fusion Compiler), static timing analysis...
mask layout from Cadence, Synopsys, Luceda, and Klayout Familiarity with the semiconductor fabrication process Experience... from Synopsys, Cadence, Luceda, and Ansys What's in it for you: Be part of a fast paced and dynamic team Very competitive...
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At-Synopsys,-we-want-talented-people-of-every-background-to-feel-valued-and-supported-to-do-their-best-work.-Synopsys...);" In-addition-to-the-base-salary,-this-role-may-be-eligible-for-an-annual-bonus,-equity,-and-other-discretionary-bonuses.-Synopsys...
signoff and at least one ASIC tape-out. Good understanding of RTL to GDS flow Proficiency using Synopsys Primetime... (or Cadence Tempus) for timing analysis and Synopsys Design Compiler (or Cadence Genus) for synthesis Ability to work with large...