Senior Lead Engineer - PD

) Routing Timing closure Physical verification Experience with EDA tools such as: Synopsys ICC2 / Fusion Compiler Cadence...

Lugar: Fremont, CA | 12/03/2026 18:03:36 PM | Salario: S/. $15000 - 18000 per year | Empresa: Quest Global

EMIR Technical Lead

to signoff). Industry-standard EDA tools (e.g., Redhawk/Voltus, Totem/Voltus-FI, Synopsys IC Compiler/Fusion, Cadence Innovus...

Lugar: San Jose, CA | 12/03/2026 01:03:05 AM | Salario: S/. No Especificado | Empresa: Altera

Senior Design Verification Engineer

to verify their design. Their design is in Verilog;you’ll use System Verilog to debug. You’ll run simulations using Synopsys..., basic circuits, and computer architecture. - You have used a tool like Synopsys, Cadence, or Mentor to run simulations...

Lugar: Westborough, MA | 12/03/2026 00:03:23 AM | Salario: S/. $108500 - 160510 per year | Empresa: Marvell

IP Design Verification Engineer

. Experience with verification tools such as Synopsys VCS, Cadence Xcelium, or Mentor Questa Experience with creating directed...

Lugar: Hillsboro, OR | 11/03/2026 20:03:42 PM | Salario: S/. No Especificado | Empresa: Intel