Physical Design Engineer for Core IP

circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design... and formal equivalence Familiar with Synopsys tool suite (Fusion compiler, ICC2, PrimeTime) or Cadence (genus/innovus...

Lugar: Hillsboro, OR | 28/05/2026 01:05:57 AM | Salario: S/. No Especificado | Empresa: Intel

Principal SoC Design Engineer

technical leadership in driving design methodology evolution and tool adoption (Synopsys DC, Genus, Verdi). GlobalFoundries...

Lugar: Texas | 24/05/2026 01:05:55 AM | Salario: S/. No Especificado | Empresa: GlobalFoundries