background using SystemVerilog/Verilog. Hands-on experience with Synopsys HAPS, Protium, Palladium, or other FPGA/emulation...
simulation Experience in specifying timing constraints with several clock domains and modes Basic experience with Synopsys...
Sigrity, Keysight ADS, or similar) Experience with SPICE simulation tools (e.g. Ansys Nexxim, Synopsys HSPICE, Cadence...
implementation for 3nm and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass... Tessent, Cadence Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools...
-standard EDA tools for design and simulation such as Cadence, Synopsys, Ansys etc. Basic scripting and automation using PERL...
closure;collaborate with the Backend/Mid-end teams to support Synthesis, SDC (Synopsys Design Constraints) generation, STA...
closure;collaborate with the Backend/Mid-end teams to support Synthesis, SDC (Synopsys Design Constraints) generation, STA...
and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion... Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools: VCS Mismatch...
Hands-on experience with industry-standard simulation tools including Synopsys VCS, Cadence Incisive/Xcelium, or Mentor...
improvements - Proficiency with multiple verification platforms (Cadence, Synopsys, Mentor/Siemens) - Experience...