Digital Designer — CPU Subsystem (RTL & Verification) (Temporary Assignment)
, and the surrounding interconnect logic - and drive their verification from unit-level testing through subsystem-level..., UVM agents, SystemVerilog assertions, coverage models - and drive coverage closure to tape-out quality. Collaborate...
Lugar: Leuven, Flemish Brabant | 03/06/2026 19:06:24 PM | Salario: S/. No Especificado | Empresa: Imec