Senior Digital Design Engineer (FPGA/ASIC)
front-end checks (lint, CDC/RDC, constraint reviews). Required Education Master’s or Ph.D. in Electrical Engineering.... Familiarity with front-end flows (synthesis, STA, lint, CDC/RDC). Strong debug skills using waveforms, logs, and implementation...
Lugar: Lint, Antwerp | 11/02/2026 02:02:05 AM | Salario: S/. No Especificado | Empresa: Paradromics, Inc.