Empleos de Ips - Trabajos de Ips - Contrato: Training

FY27 Intern- Integration of a RISC-V CPU into a Cache-Coherent Emulation Platform - Sophia, 6 months

is used to verify interoperability between key system IPs, including CPUs, the network-on-chip (NoC), and DDR controllers. It... and how they interact with other system IPs. RISC-V architecture study Core Activities Collaborate with the CPU team to import...

Lugar: Alpes-de-Haute-Provence - Bainbridge, North Yorkshire | 31/10/2026 03:10:32 AM | Salario: S/. No Especificado | Empresa: Qualcomm

Stage IngÃ©nieur : Conception pour le test (DFT) / Conception numÃ©rique (F/H)

Use AI and scripting to automate the DFT IPs integration in a System On Chip or a sub-system Use AI and scripting...

Lugar: Valbonne, Alpes-Maritimes - Sophia-Antipolis, Alpes-Maritimes | 24/09/2026 02:09:30 AM | Salario: S/. No Especificado | Empresa: NXP Semiconductors

of digital IPs. We are recruiting a final-year engineering intern for a 6-month internship to design and develop an AI-based... IPs. Compare results against traditional manual integration methods. Evaluate improvements in terms of productivity...

Lugar: Valbonne, Alpes-Maritimes - Sophia-Antipolis, Alpes-Maritimes | 17/09/2026 23:09:39 PM | Salario: S/. No Especificado | Empresa: NXP Semiconductors

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Empleos de IpsEmpleos de Ips - Trabajos de Ips - Contrato: Training

FY27 Intern- Integration of a RISC-V CPU into a Cache-Coherent Emulation Platform - Sophia, 6 months

Stage IngÃ©nieur : Conception pour le test (DFT) / Conception numÃ©rique (F/H)

Stage IngÃ©nieur : Application de l'Intelligence Artificielle Ã l'intÃ©gration de blocs RTL (ASIC/FPGA) (H/F)