CDI] Senior FPGA prototyping engineer
, Sophia Antipolis), Spain (Barcelona) and Italy (Bologna) 💻 About the role To validate our first tape-out...
Lugar: Grenoble, Isère | 04/02/2026 02:02:00 AM | Salario: S/. No Especificado | Empresa: SiPearl
, Sophia Antipolis), Spain (Barcelona) and Italy (Bologna) 💻 About the role To validate our first tape-out...
for bandwidth and noise Wafer‑level test structure design and tape‑out experience Knowledge of TIAs, impedance matching, high...
Wafer‑level test structure design and tape‑out experience Hands‑on experience with modeling and simulation tools...
tool settings for timing closure and sign-off settings before tape-out Perform STA Sign-off at top level Work in close...