Digital Design Verification Engineer

, Simvision) or equivalent Synopsys verification tool chain. Ideal fit Asic design and mixed signal verification knowledge...Role Overview Design Verification Engineer with expertise in System Verilog, UVM methodology. Experience in ASIC...

Lugar: Dresden, Sachsen | 28/04/2026 17:04:23 PM | Salario: S/. No Especificado | Empresa: Ferroelectric Memory