AMS Verification Engineer

and implementing SystemVerilog Assertions (SVA). Collaborating with cross-functional teams, including design, test, and verification... Assertions (SVA). Fluency in scripting languages such as Perl or Python. Experience generating functional models for analog...

Lugar: Bayern | 29/10/2026 22:10:27 PM | Salario: S/. No Especificado | Empresa: IC Resources

AMS Verification Engineer

and implementing SystemVerilog Assertions (SVA). Collaborating with cross-functional teams, including design, test, and verification... Assertions (SVA). Fluency in scripting languages such as Perl or Python. Experience generating functional models for analog...

Lugar: Bayern | 29/10/2026 18:10:17 PM | Salario: S/. No Especificado | Empresa: IC Resources

Verification Engineer

by property-based test generation rather than fixed directed vectors.Write SystemVerilog Assertions (SVA) to catch protocol...-based test harnesses, cross-checks RTL against formally-specified golden models, and wires up both SVA and native...

Lugar: Baden-Württemberg | 25/10/2026 17:10:51 PM | Salario: S/. No Especificado | Empresa: Ubitium GmbH

Verification Engineer

by property-based test generation rather than fixed directed vectors.Write SystemVerilog Assertions (SVA) to catch protocol... both SVA and native SystemVerilog covergroups. If you have opinions on how verification should be done, there’s real room...

Lugar: Karlsruhe, Baden-Württemberg | 21/10/2026 17:10:49 PM | Salario: S/. No Especificado | Empresa: Ubitium GmbH