Digital Design Verification Engineer

Synopsys verification tool chain. Problem Solving and Communication skills. Responsibilities Develop and maintain UVM.... Execute both block and system levels verification. Simulate and debug using Cadence/Synopsys tools for design inspection...

Lugar: Dresden, Sachsen | 28/04/2026 17:04:09 PM | Salario: S/. No Especificado | Empresa: Ferroelectric Memory GmbH

Senior ASIC/SoC Development Engineer

and strong practical experience with ASIC (Application-Specific Integrated Circuit) implementation and associated EDA tools (Synopsys... and verification: respective EDA tools (Siemens, Synopsys, Cadence), related design languages (VHDL, System Verilog...

Lugar: Deutschland | 18/02/2026 23:02:06 PM | Salario: S/. No Especificado | Empresa: Nokia