, C models, and Vertical/Horizontal re-usable Verification Environments. Verifying sensor algorithms RTL for ASIC... Implementing C model integration within UVM framework. Writing SystemVerilog assertions Debugging, verifying, optimizing...
-exact modeling, RTL co-simulation, and functional verification collaboration with design teams Proficiency in C (embedded... across processing elements on the SoC Own simulation-to-RTL validation flows: develop bit-exact reference models, collaborate with RTL...
such as UVM and Formal Verification Developing Testbenches and Verification Components such as UVCs, C models, and Vertical... development based on Design documents and interaction with design/systems engineers Implementing C model integration within UVM...