like Jasper or VC_Formal is a plus Experience with SystemC and Matlab are a plus. Gate level Simulation debug and usage of power...
and BFM development, functional and gate-level verification, and coverage closure. Debugging and root causing bugs caught...
scenarios. Execute power-aware simulations, gate-level simulations, and formal verification. Collaborate cross-functionally...
such as Simulators, Coverage collection, Gate-level Simulation, Waveform viewers, and Formal Proof Tools. Ability to develop and work...
Verification Methodologies and Tools such as Simulators, Coverage collection, Gate-level Simulation, Waveform viewers, and Formal...
static timing analysis on gate-level PNR netlists, provide feedback to RTL, Synthesis and Physical Design teams to improve...
Cleaner required for the Education & Rights Resource Centre in Churchfield and the Gate Lodge in St Marys Campus...
, analytical technology upgrades, and facility modifications. Lifecycle Management: Execute projects following strict stage-gate...
, and claims prior to submission. Support gate-to-gate NPD workflow by tracking tasks, timelines, risks, and approvals...
Working with design team on selecting use-cases for power integrity sign-off, and performing power analysis on PD gate...