We are seeking a Formal Verification Engineer to join our team. In this role, you will leverage advanced formal verification techniques to ensure the correctness and performance of high-end RISC-V cores. You will collaborate closely with ar...
A leading technology firm in Mexico is seeking a Formal Verification Engineer to leverage advanced techniques ensuring the performance of RISC-V cores. This role involves collaborating closely with architects and RTL engineers to develop in...
A leading tech company is looking for a CPU Design Engineer in Mexico, Jalisco, Región Centro. This role involves designing and implementing high-performance execution units in CPUs, working on microarchitecture, and collaborating with team...
A technology firm located in Mexico seeks a skilled Performance and Power Modeling Engineer to lead efforts in modeling and optimizing the silicon development lifecycle. You will analyze workloads, identify inefficiencies, and collaborate w...
We are seeking a Senior CPU Design Engineer to join our team. In this role, you will be responsible for designing and implementing high-performance execution units in CPU, optimizing for power, performance, and area (PPA). You will work clo...
We are seeking a CPU Design Engineer to join our team. In this role, you will be responsible for designing and implementing high-performance execution units in CPU, optimizing for power, performance, and area (PPA). You will work closely wi...
We are seeking a Physical Design Engineer to drive CPU power, performance, and area (PPA) optimization at advanced technology nodes. You will be responsible for physical implementation, collaborating with RTL, and logic design teams to deli...
A technology startup in Guadalajara, Mexico is looking for a Physical Design Engineer to optimize CPU power, performance, and area (PPA). The role involves physical implementation from RTL-to-GDSII, working closely with RTL designers to enh...
We are seeking a skilled and motivated Performance and Power (PnP) Modeling Engineer to lead modeling, analysis, and optimization efforts across the full silicon development lifecycle. This role spans architectural modeling, RTL-level analy...