Atom CPU Layout Design Intern

implementation flows, including floorplanning, routing, design rule checks (DRC), and layout vs. schematic verification (LVS). EDA...

Lugar: Guadalajara, Jal. | 07/03/2026 02:03:40 AM | Salario: S/. No Especificado | Empresa: Intel

Layout Design Engineer

manufacturability and yield performance Quality Assurance and Verification Execute comprehensive DRC-LVS verification to ensure... and integration EDA tools (DRC/LVS verification, CMOS processes) Experience with basic integrated circuit operation fundamentals...

Lugar: Guadalajara, Jal. | 19/02/2026 03:02:54 AM | Salario: S/. No Especificado | Empresa: Intel

Layout Design Engineer

compliance with design rules using DRC/LVS verification methodologies Implement fill strategies to meet design rules... technology Experience with industry-standard EDA tools, DRC/LVS verification, and CMOS process technologies Experience...

Lugar: Guadalajara, Jal. | 13/02/2026 02:02:46 AM | Salario: S/. No Especificado | Empresa: Intel
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