Trim Engineer

and DV testing with minimal direction. Demonstrated ability to understand and apply one or more basic problem solving...

Lugar: Querétaro, Qro. | 11/02/2026 02:02:29 AM | Salario: S/. No Especificado | Empresa: Adient

Low Power Design Engineer

, power aware DV and high speed clocking desired. Proficiency in Verilog/System Verilog coding, verification techniques...

Lugar: Tijuana, B.C. | 07/02/2026 19:02:19 PM | Salario: S/. No Especificado | Empresa: NAPS