Layout Design Engineer

in: Device-level CMOS analog/memory custom layout design Advanced process nodes (7nm and beyond) ICC, Fusion compilers...

Lugar: Guadalajara, Jal. | 18/02/2026 21:02:47 PM | Salario: S/. No Especificado | Empresa: Intel

Layout Design Engineer

and methodologies Experience with ICC, Fusion Compiler, and ICWBEV+ design tools Experience in scripting languages (Python, SKILL...

Lugar: Guadalajara, Jal. | 13/02/2026 00:02:30 AM | Salario: S/. No Especificado | Empresa: Intel
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