Emulation Engineering Intern

and optimization. RTL design. Experience with emulators such as Synopsys ZeBu, Cadence Palladium or Mentor Graphic Veloce for large... scale designs. Experience with RTL design, Verilog and simulation, debug tools such as Verdi, System Verilog based...

Lugar: Guadalajara, Jal. | 04/12/2025 01:12:51 AM | Salario: S/. No Especificado | Empresa: Intel