Fpga Software Enabling Engineer

Design (Verilog or VHDL, RTL simulation, Static Timing Analysis (timing closure). - System Level. - FPGA or ASIC experience...

Lugar: Jalisco | 15/12/2025 18:12:25 PM | Salario: S/. No Especificado | Empresa: Intel

Project Manager

, within budget and at the required level of quality. Evaluate the outcomes of the project as established during the planning phase...

Lugar: Jalisco | 15/12/2025 18:12:08 PM | Salario: S/. No Especificado | Empresa: Create For Life

Service Desk Level 1

Now, Archer among others (desirable). - Academic Level: Completed or on pause career in Engineering, Computer Engineering... with business partners and other areas to ensure SLAs (Service Level Agreements). - Expertise in data collection for management...

Lugar: Veracruz, Ver. | 15/12/2025 18:12:01 PM | Salario: S/. No Especificado | Empresa: Kyndryl

Apple (Macos/Ios) Platform Engineer

experience. - Provide Level 3 engineering support to ensure customer issues are resolved relating to MacOS, App Compatibility... Level 3 engineering support to ensure customer issues are resolved relating to MacOS, App Compatibility, Browser...

Lugar: Veracruz, Ver. | 15/12/2025 18:12:01 PM | Salario: S/. No Especificado | Empresa: Takeda