Cpu Pre-Silicon Verification Engineer
systematic coverage‐driven closure. Implement high‐quality stimulus and assertion‐based verification (SVA) to validate complex...
Tech Ip Library Characterization Engineer
, Verilog/ System Verilog, RTL design verification, System Verilog Assertion (SVA), Design for Test, BIST modeling experience...
Lugar: Baja California | 24/08/2026 17:08:02 PM | Salario: S/. No Especificado | Empresa: Qualcomm
Tech IP Library Characterization Engineer
design flow, RTL design/coding, logic design, Verilog/ System Verilog, RTL design verification, System Verilog Assertion (SVA...
Lugar: Tijuana, B.C. | 04/08/2026 21:08:45 PM | Salario: S/. No Especificado | Empresa: Qualcomm
SoC/IP Design Verification Engineer
, and implement closure strategies. Leverage assertions (SVA) and formal where appropriate to strengthen verification quality..., LP/DDR, USB, MIPI, I3C, SPI/I2C, Ethernet;integrating and customizing VIP. Assertion-based verification (SVA...
Lugar: Zapopan, Jal. | 25/07/2026 01:07:18 AM | Salario: S/. No Especificado | Empresa: Intel