Design engineer

We're Hiring! ?? Senior Circuit Design Engineer - DRAM Design ?? Where?: Guadalajara, México ???? If you're...) ? Fluent English level (Written and Spoken) ? Experience with scripting languages like Python, Perl, Verilog, or UVM...

Lugar: Guadalajara, Jal. | 31/10/2024 18:10:27 PM | Salario: S/. No Especificado | Empresa: Manpower

Senior Design Verification Engineer - DFT

Experis, ManpowerGroup, hiring for AI enablers for?Micron's new product development facility in Guadalajara, Mexico... and analyzing pre-silicon designs. Develop SystemVerilog testbench infrastructure (UVM and constrained random verification...

Lugar: Tlaquepaque, Jal. | 11/10/2024 17:10:20 PM | Salario: S/. No Especificado | Empresa: Manpower

Senior Circuit Design Engineer

Experis, ManpowerGroup, hiring for AI enablers for?Micron's new product development facility in Guadalajara, Mexico... communication skills for sharing ideas. Experience with scripting languages (Python, Perl, Verilog, UVM, etc.). What Sets...

Lugar: Tlaquepaque, Jal. | 11/10/2024 17:10:02 PM | Salario: S/. No Especificado | Empresa: Manpower

Analog Verification Engineer

Experis, ManpowerGroup, hiring for AI enablers for?Micron's new product development facility in Guadalajara, Mexico... circuit design. Familiarity with digital verification (e.g., SystemVerilog, UVM). Excellent communication and problem...

Lugar: Tlaquepaque, Jal. | 25/09/2024 17:09:36 PM | Salario: S/. No Especificado | Empresa: Manpower