SoC Pre-Silicon Verification Engineer

-standard verification methodologies such as UVM or System Verilog or Digital Design Advance English level... Qualifications: 3+ years System Verilog and UVM experience 2+ years in: Python for test automation. Simulation tools (VCS...

Lugar: Guadalajara, Jal. | 10/05/2026 20:05:03 PM | Salario: S/. No Especificado | Empresa: Intel

SoC Debug Engineer

verification concepts (testbenches, assertions/SVA;UVM familiarity is a plus). Familiarity with JTAG/TAP, boundary scan...

Lugar: Guadalajara, Jal. | 01/05/2026 23:05:17 PM | Salario: S/. No Especificado | Empresa: Intel

SoC Pre-Silicon Verification Engineer

such as UVM or System Verilog or relevant experience in Silicon Validation. Advance English level. Preferred Qualifications...: 4+ years System Verilog and UVM experience 3+ years in Python for test automation ARM-based SoC or equivalent...

Lugar: Guadalajara, Jal. | 19/04/2026 20:04:40 PM | Salario: S/. No Especificado | Empresa: Intel
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