Lead MTS Logic Design

Implementation: RTL design, lint, clock domain crossing (CDC) analysis, synthesis, IP release Verification: work with verification...

Lugar: Vught, Noord-Brabant | 11/02/2026 21:02:52 PM | Salario: S/. No Especificado | Empresa: Rambus

Lead Logic Design Engineer

Implementation: RTL design, lint, clock domain crossing (CDC) analysis, synthesis, IP release Verification: work with verification...

Lugar: Vught, Noord-Brabant | 11/02/2026 21:02:29 PM | Salario: S/. No Especificado | Empresa: Rambus

Team Lead Digital Verification

synthesis, timing, DFT issues for the ASIC implementation. You understand all design integration activities like Lint, CDC... specification and validation methodology. Strong knowledge of clock domain crossing (CDC) techniques. Understanding of digital...

Lugar: Delft, Zuid-Holland | 20/01/2026 23:01:13 PM | Salario: S/. No Especificado | Empresa: Qualinx

Lead MTS Logic Design

, have/encourage innovative ideas/patents for current and future products Implementation: RTL design, lint, clock domain crossing (CDC...

Lugar: Países Bajos | 15/01/2026 21:01:35 PM | Salario: S/. No Especificado | Empresa: microTECH Global