ASIC Security Staff Engineer

technological innovation. You Are: You are a passionate and skilled ASIC Digital Design Engineer with knowledge in RTL design... Intelligence, and Automotive. What You'll Be Doing: Designing and implementing RTL in Verilog and/or System Verilog...

Lugar: Eindhoven, Noord-Brabant | 21/02/2026 22:02:31 PM | Salario: S/. No Especificado | Empresa: Synopsys

FPGA Architect

across hardware, software, and test domains Own the full FPGA lifecycle: architecture, RTL design, simulation, synthesis, timing...

Lugar: Países Bajos | 18/02/2026 23:02:54 PM | Salario: S/. No Especificado | Empresa: microTECH Global

Senior Digital Design Engineer

(RTL) design from the micro-architecture specification using Verilog or SystemVerilog as the HDL. Developing standalone... test benches to verify the RTL behaviour. Writing and verifying SystemVerilog Assertions (SVA) for a design. Writing...

Lugar: Países Bajos | 18/02/2026 20:02:14 PM | Salario: S/. No Especificado | Empresa: microTECH Global

Lead Logic Design Engineer

Implementation: RTL design, lint, clock domain crossing (CDC) analysis, synthesis, IP release Verification: work with verification...

Lugar: Vught, Noord-Brabant | 12/02/2026 01:02:27 AM | Salario: S/. No Especificado | Empresa: Rambus