Physical Design Engineer, Senior to Staff Level
, Placement, Clock Tree Synthesis (CTS), and Routing. Timing Analysis & Closure: Perform Static Timing Analysis (STA) to identify...
, Placement, Clock Tree Synthesis (CTS), and Routing. Timing Analysis & Closure: Perform Static Timing Analysis (STA) to identify...
problem-solving and cross-functional communication skills Experience with low-power design techniques and clock/power domain...
simulations, and compliance testing. Experience qualifying PMICs, voltage regulators (VRs), clock buffers, flash memory...
. Experience qualifying PMICs, voltage regulators (VRs), clock buffers, flash memory, and connectors for use in complex card.... Expertise in clock distribution, power distribution, SMBus, PMBus, SPI, PWM/Tach, and BMC integration. Proficient in schematic...
validation. Work with PD teams to meet PPA targets via pipeline design, timing closure strategies, clock/power domain planning...
) and verification simulation tool(VCS). Familiarity with SOC basic architecture(clock,reset,power rail,IO pad,package) Understanding...
/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller...
/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS...
Front-End, PLL, reference generation, clock distribution) required to implement the architecture in advanced FinFET process...
-speed SerDes, as well as supporting analog IPs like analog bias, clock buffer and generator, process monitor, temperature...