on early-stage investigation, proof-of-concept development, and architectural evaluation. You’ll take emerging ideas and ASIC... environments, and carry out hands-on evaluation of mixed-signal devices. You’ll work closely with architects, ASIC designers...
of complex digital and mixed-signal ASIC designs using advanced verification methodologies. Key responsibilities Develop... and execute comprehensive verification plans for complex mixed-signal ASIC designs Create and maintain UVM-based SystemVerilog...
while minimising the risk of re-spins. The ASIC team is involved in every stage of the development flow—from requirements capture...) Experience in digital ASIC design and verification, including: Defining functional requirements for verification environments...
. Desired experience Extensive knowledge of ASIC physical design from RTL to GDSII Hands-on experience with EDA tools...
group responsible for shaping and delivering digital subsystems across ASIC and FPGA platforms. You’ll be involved... checks such as LINT, CDC, and formal analysis. Over time, you’ll deepen your exposure to industry-standard ASIC and FPGA...
methodologies and tools Experience with UVM (Universal Verification Methodology) for FPGA/ASIC verification Familiarity...
in verifying complex designs (preferably in high volume applications) – FPGA or ASIC Familiarity with SerDes and high-level...
A leading international space technology organisation is continuing to expand its advanced ASIC capability... required: Strong background as a Senior Physical Design Engineer within ASIC development Proven experience across advanced node physical design...
verification process applied in CPU and/or ASIC environments System Verilog, Python, C++, Linux UVM SVA LLVM, GCC SGE...
to find root causes of deep and complex issues Experience of the verification process applied in CPU and/or ASIC environments...