Senior CPU Design Verification Engineer

verification methodology. Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs... techniques, and the full verification life cycle. Experience with performance verification of ASICs and ASIC components...

Lugar: London | 12/09/2026 22:09:32 PM | Salario: S/. No Especificado | Empresa: QualityAI