Senior Verification Engineer
-signal design verification Strong proficiency in SystemVerilog, UVM, and leading simulation tools (e.g., Synopsys VCS...
Lugar: Edinburgh | 17/03/2026 19:03:22 PM | Salario: S/. No Especificado | Empresa: IC Resources
Layout Engineer
fabrication processes. Automate: Develop and refine layout workflows using tools such as KLayout, L-Edit, Cadence, Synopsys...
Lugar: England | 06/03/2026 18:03:53 PM | Salario: S/. No Especificado | Empresa: Oxford Quantum Circuits
Digital RTL Design Engineer
Experience with industry-standard EDA tools (e.g., Vivado or Cadence, Synopsys, or Mentor Graphics) Strong problem-solving...
Lugar: United Kingdom | 25/02/2026 18:02:17 PM | Salario: S/. No Especificado | Empresa: microTECH Global
Principal Digital IC Design Engineer
closure, DFT insertion, and ECO from Synopsys or Cadence. Experience with CMOS process technologies from 180nm down to 28nm...
Lugar: United Kingdom | 18/02/2026 19:02:26 PM | Salario: S/. No Especificado | Empresa: microTECH Global
Senior Formal Verification Engineer
;contribution to subsystem-level sign-off Proficiency with formal tools: Cadence JasperGold, Synopsys VC Formal;familiarity...
Lugar: Cambridge | 31/01/2026 03:01:57 AM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices
FPGA Engineer - Submarines
: Siemens - QuestaSim / ModelSim Siemens - Questa PropCheck Siemens - FormalPro Synopsys - Synplify Pro IBM® Engineering...
Lugar: Derby | 23/01/2026 23:01:50 PM | Salario: S/. No Especificado | Empresa: Rolls-Royce
DFT Engineer
tools Knowledge of ATPG pattern verification and gate-level simulation flows using Synopsys VCS and Verdi or other EDA...
Lugar: Cambridge, Gloucestershire - Bristol Area | 22/01/2026 21:01:43 PM | Salario: S/. No Especificado | Empresa: Graphcore
Senior Engineer, Digital Design Engineering
, scan pattern debugging Familiarity with Cadence and Synopsys design tools Experience debugging ICs and associated...
Lugar: Edinburgh - Freer, TX | 22/01/2026 01:01:17 AM | Salario: S/. No Especificado | Empresa: Analog Devices
Principal Silicon Design Verification Engineer
. Strong problem-solving skills. Experience of Synopsys functional verification tools would be an advantage. Experience of full chip...
Lugar: Penicuik, Midlothian | 18/01/2026 00:01:45 AM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices
Design For Test
, Cell Aware etc. Knowledge of ATPG pattern verification and gate-level simulation flows using Synopsys VCS and Verdi... based DFT DRC checks at RTL level would be a plus. Experience with Synopsys Design Compiler/Test Compiler/Fusion Compiler...
Lugar: Cambridge | 16/01/2026 20:01:10 PM | Salario: S/. No Especificado | Empresa: Advanced Micro Devices