, scan pattern debugging Familiarity with Cadence and Synopsys design tools Experience debugging ICs and associated...
. Strong problem-solving skills. Experience of Synopsys functional verification tools would be an advantage. Experience of full chip...
, Cell Aware etc. Knowledge of ATPG pattern verification and gate-level simulation flows using Synopsys VCS and Verdi... based DFT DRC checks at RTL level would be a plus. Experience with Synopsys Design Compiler/Test Compiler/Fusion Compiler...
verification. Strong proficiency in SystemVerilog, UVM, and simulation tools (Synopsys VCS, Cadence Xcelium). Solid understanding...