FPGA Design Verification Engineer

: · Strong understanding of FPGA, ASIC, RTL design principles and architectures. · Proficiency in System Verilog and UVM verification...

Lugar: Mountain View, CA | 31/01/2026 20:01:25 PM | Salario: S/. $101000 - 152000 per year | Empresa: UST

Senior Analog Design Engineer

based on the requirements of the organization and/or your performance. #UST #LI-MK2 Skills: asic design,analog mixed...

Lugar: Santa Clara, CA | 25/01/2026 03:01:36 AM | Salario: S/. No Especificado | Empresa: UST

FPGA Design Verification Engineer

: · Strong understanding of FPGA, ASIC, RTL design principles and architectures. · Proficiency in System Verilog and UVM verification...

Lugar: Mountain View, CA | 24/01/2026 20:01:28 PM | Salario: S/. $101000 - 152000 per year | Empresa: UST

Game Tester

-RK2 Skills: asic verification,pc platform,test automation,functional testing, About Company: UST is a global...

Lugar: Folsom, CA | 09/01/2026 00:01:15 AM | Salario: S/. $44000 - 66000 per year | Empresa: UST
1