Personal Injury Paralegal

, and insurance companies Preparing deposition, mediation, and trial materials Managing court calendars, filing deadlines... for professional growth and hands-on experience Convenient office location: one block from the "A" Train with Q11, Q21, and Q41 bus...

Lugar: Queens, NY | 22/07/2026 21:07:14 PM | Salario: S/. $60000 - 75000 per year | Empresa: Sullivan & Galleshaw, LLP

Personal Injury Litigation Paralegal

, and insurance companies Preparing deposition, mediation, and trial materials Managing court calendars, filing deadlines, and case... growth and hands-on experience Convenient office location: one block from the "A" Train with Q11, Q21, and Q41 bus routes...

Lugar: Queens, NY | 22/07/2026 21:07:34 PM | Salario: S/. $70000 - 85000 per year | Empresa: Sullivan & Galleshaw, LLP

Sr. SRAM Layout Design Engineer

debugging using Calibre, ICV, or similar physical verification tools. · Experience with floorplanning, block-level routing..., UST has worked side by side with the world’s best companies to make a real impact through transformation. Powered...

Lugar: Santa Clara, CA | 22/07/2026 20:07:53 PM | Salario: S/. $101000 - 152000 per year | Empresa: UST

Design Verification Manager

and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge... accountability. Allocating resources effectively across multiple parallel chip/block schedules. Verification Strategy...

Lugar: Sunnyvale, CA | 22/07/2026 20:07:05 PM | Salario: S/. No Especificado | Empresa: Hewlett Packard Enterprise

Behavior Technician (BT) / Registered Behavior Technician (RBT)

at state minimum wage for applicable in-home sessions Block Scheduling – Our centralized scheduling team works to maximize... and teamwork skills Why Join BlueSprig? At BlueSprig and our affiliated companies, we are on a mission to change the world...

Lugar: Katy, TX | 22/07/2026 20:07:04 PM | Salario: S/. $20 - 22 per hour | Empresa: BlueSprig

Fpga Design Engineer

(VHDL/Verilog/SystemVerilog), timing closure, and block design development are essential. This role involves driving FPGA... integration across multiple FPGA families. Define and document FPGA architecture, including block diagrams, clocking strategies...

Lugar: Melbourne, FL | 22/07/2026 19:07:09 PM | Salario: S/. No Especificado | Empresa: Actalent

Staff Electrical Engineer

. Proven capability to critically analyze third-party electrical schematics, PCB layouts, and block diagrams to enforce design... in engineering and sciences services and talent solutions. We help visionary companies advance their engineering and science...

Lugar: Mountain View, CA | 22/07/2026 19:07:54 PM | Salario: S/. $70 - 80 per hour | Empresa: Actalent