Engineering Intern - ASIC DFT (Spring 2027 Co-Op)

AI , generation of verification summary and dashboard results for block level and chip level. In this role you will developing Design... for Test Methodology for NextGen Rivian Autonomy Processor. Responsibilities Creating Block level, Chip Level Verification...

Lugar: Palo Alto, CA | 01/10/2026 18:10:21 PM | Salario: S/. $45 - 51 per hour | Empresa: Rivian

Supervisor Tailings

block-cave, underground mining complex feeding a concentrator with a current capacity of approximately 32,000 metric tons...

Lugar: Parshall, CO | 01/10/2026 17:10:39 PM | Salario: S/. $1450 mensual | Empresa: Freeport-McMoRan

Senior IP Design Verification Engineer

verification of complex flows at subsystem, IP or block level. Learn about the design and interact with partner teams to define... for a full product cycles from definition to silicon, including writing IP/block or subsystem level test plans, developing tests...

Lugar: Hillsboro, OR | 30/09/2026 22:09:03 PM | Salario: S/. No Especificado | Empresa: Microsoft

Embedded Firmware Engineer

or block diagrams, test logs, and release checklists under guidance. Participate in peer code and design reviews...

Lugar: Indianapolis, IN | 30/09/2026 20:09:41 PM | Salario: S/. No Especificado | Empresa: V2X