Design Verification Engineer
memory arrays. ● Tools: Cadence Virtuoso, Spectre, Verilog-AMS, Synopsys CustomSim, Calibre, mixed-signal simulation...
Lugar: Palo Alto, CA | 28/10/2025 18:10:31 PM | Salario: S/. $160000 - 180000 per year | Empresa: Quest Global