Senior or Principal ASIC Design Engineer Key Responsibilities: Design and implement digital circuits using HDL (Verilog/ System Verilog) Perform synthesis, timing analysis, Lint, formal equivalence, Clock Domain Crossing (CDC) analysis...
Principal Digital Signal Processing (DSP) Engineer Key Responsibilities: Developing new DSP algorithms to be used in optical transceivers. Documenting design details and collaborating with ASIC, firmware, and verification teams to reli...
with remote options, 401K employer match) DESIGN VERIFICATION GROUP on LinkedIn: #DesignVerification #SoC #UVM #Chisel...
Senior or Principal ASIC Design Engineer Key Responsibilities: Design and implement digital circuits using HDL (Verilog/ System Verilog) Perform synthesis, timing analysis, Lint, formal equivalence, Clock Domain Crossing (CDC) analysis...
with remote options, 401K employer match) DESIGN VERIFICATION GROUP on LinkedIn: #DesignVerification #SoC #UVM #Chisel...
with remote options, 401K employer match) DESIGN VERIFICATION GROUP on LinkedIn: #DesignVerification #SoC #UVM #Chisel...
Senior or Principal ASIC Design Engineer Key Responsibilities: Design and implement digital circuits using HDL (Verilog/ System Verilog) Perform synthesis, timing analysis, Lint, formal equivalence, Clock Domain Crossing (CDC) analysis...
with remote options, 401K employer match) DESIGN VERIFICATION GROUP on LinkedIn: #DesignVerification #SoC #UVM #Chisel...
Technical Director, Test Development Engineering Location: Irvine, CA (onsite) US Citizen or US Permanent Resident preferred Full-time Employee + Bonus, Benefits, 401k, Stock Options In this role, you will be responsible for Test Devel...
with remote options, 401K employer match) DESIGN VERIFICATION GROUP on LinkedIn: #DesignVerification #SoC #UVM #Chisel...