Neuromorphic Front-End Silicon Lead

of experience with RTL design (Verilog/SystemVerilog) and modern ASIC flows (synthesis, timing closure, CDC/RDC, formal, DFV). 3... to manage both the design and verification of our neuromorphic chiplets and IP. This principal-level role calls for a talented...

Lugar: Hillsboro, OR | 05/09/2026 02:09:42 AM | Salario: S/. No Especificado | Empresa: Intel

Civil Project Manager/Engineer

About Us CivilDesignConcepts is an Employee-Owned value-add Engineering firm offering a full array of land planning... agencies and other important stakeholders, the production of all elements of the civildesign and project deliverables, the...

Lugar: Asheville, NC | 04/08/2026 22:08:22 PM | Salario: S/. No Especificado | Empresa: Civil Design Concepts