, Fault Tree Analysis, Preliminary Hazard Analysis, System Safety Analysis, and Software Hazard Analysis. Perform... quantitative and qualitative risk assessments and trade studies to optimize design choices and recommend controls. Coordinate...
, perform design effectiveness and operating effectiveness testing, and identify potential opportunities for improvement...) or equivalent Completion of professional auditor training Causal Evaluation Certification (e.g., Barrier Analysis, Fault Tree, 5...
design, placement, clock tree synthesis (CTS), and routing using Synopsys Fusion Compiler. Timing Closure: Perform rigorous...Physical Design Engineer (ASIC/SoC) – with Active Secret Clearance Clearance Requirement: Active Secret Clearance...
grid design, placement, clock tree synthesis (CTS), and routing using Synopsys Fusion Compiler. Timing Closure: Perform...Physical Design Engineer (ASIC/SoC) - Onsite Clearance Requirement: Active Secret Clearance (or ability to obtain...
. Conduct root cause investigations using structured problem-solving methodologies such as 5 Why, Fishbone Analysis, Fault Tree..., CAPAs, design changes, supplier issues, and field actions. Ensure alignment of risk management activities with applicable...
Construction/volume calculations Design surveys Mobile lidar Scan-to-BIM/terrestrial lidar Survey control Tree surveys... development, route, utility, and other surveying projects. Support the Party Chief with land development, boundary, design...
and business relevance Leverage generative AI frameworks and large language models (LLMs) to design and deploy internal... and predictive analytics into clear, actionable business strategies, partnering with analysts to design rigorous A/B tests Monitor...
, overseeing synthesis, floorplanning, power grid design, place and route, clock tree synthesis, timing closure, power/signal... opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance...
grid design, placement, clock tree synthesis (CTS), and routing using Synopsys Fusion Compiler. Timing Closure: Perform...Physical Design Engineer (ASIC/SoC) - Onsite Clearance Requirement: Active Secret Clearance (or ability to obtain...
grid design, placement, clock tree synthesis (CTS), and routing using Synopsys Fusion Compiler. Timing Closure: Perform...Physical Design Engineer (ASIC/SoC) - Onsite Clearance Requirement: Active Secret Clearance (or ability to obtain...