Principal Analog Design Engineer

for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, CDRs etc. to meet key performance targets and performing design...

Lugar: Santa Clara, CA | 23/12/2025 19:12:08 PM | Salario: S/. $165630 - 248100 per year | Empresa: Marvell

Analog Engineer Intern - PhD

’s, TAH/SAH’s) Major design project experience in clock conditioning circuits (i.e., PLL’s, DLL’s, PI’s) Experience...

Lugar: Irvine, CA | 16/12/2025 18:12:15 PM | Salario: S/. $31 - 61 per hour | Empresa: Marvell

Analog Intern - PhD

technologies. Responsible for investigating and implementing circuits such as PLL, DLL, ADC, Regulators, amplifiers...

Lugar: Santa Clara, CA | 14/10/2025 21:10:13 PM | Salario: S/. $31 - 61 per hour | Empresa: Marvell
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