Memory Chip Design Engineer

world. From energizing the most competitive gaming platforms, to enabling systems to make cities safer and cars smarter... optimization, final verification up to and including tape out Running and Debugging Physical Verification flows including DRC, LVS...

Lugar: San Jose, CA | 03/02/2026 18:02:51 PM | Salario: S/. $145800 - 194400 per year | Empresa: Western Digital

ASIC Digital Design Engineer

) with congestion management. Timing closure across PVT corners. DRC, LVS, extraction and signoff. Perform RTL Verification... in the following Areas: Full Custom IC Layout Design and CAD tools Imaging Systems and Electro-Optical Components...

Lugar: USA | 05/01/2026 02:01:07 AM | Salario: S/. $141900 - 189200 per year | Empresa: Link Consulting Services

Senior CMOS IC CAD Engineer

solves tough, meaningful problems that create a safer, more secure world. Raytheon Vision Systems is seeking to hire... designers including Virtuoso, DRC/LVS/PEX/PERC verification tools, extractions, and spice simulation tools Work with CAD tool...

Lugar: Goleta, CA | 17/01/2026 00:01:34 AM | Salario: S/. $95500 - 181700 per year | Empresa: Raytheon Technologies

Principal/ Senior Principal Digital ASIC Circuit Design Engineer

Description At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives... are not only part of history, they're making history. The Northrop Grumman Mission Systems (NGMS) Advanced Processing Solutions...

Lugar: USA | 26/11/2025 18:11:46 PM | Salario: S/. $119600 - 179500 per year | Empresa: Northrop Grumman

Circuit Design Support Engineer

Description At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives... on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive...

Lugar: USA | 07/01/2026 18:01:30 PM | Salario: S/. $108800 - 163200 per year | Empresa: Northrop Grumman

Analog Design Engineer

efficiency. Carry out comprehensive post-layout verification, including Parasitic Extraction (PEX), Design Rule Check (DRC..., or a related field with advanced-level courses work in Analog Integrated Circuit, CMOS Circuit Design, RF Circuits and Systems...

Lugar: Santa Clara, CA | 05/02/2026 00:02:47 AM | Salario: S/. $156853 - 160000 per year | Empresa: OmniVision

IC CAD Engineer - Analog Mixed-Signal Flow Automation

verification tools and decks (DRC, LVS, PEX, EM/IR, ESD, etc.). Support PDK administration, including installation, regression..., or a related field. 4+ years of experience in CAD engineering for IC design. Proficiency in Cadence Virtuoso, Calibre DRC/LVS...

Lugar: San Francisco, CA | 17/01/2026 19:01:35 PM | Salario: S/. $65200 - 158550 per year | Empresa: Capgemini

CAD Engineer, AI Based Automation Development

environments Build APIs and backend systems to support AI functionalities within web applications Perform system testing... processes (STA, DRC, LVS, ERC, EMIR) a plus Experience with advanced technology nodes (n5/n3/n2) design process...

Lugar: Santa Clara, CA | 10/12/2025 21:12:21 PM | Salario: S/. $105470 - 158000 per year | Empresa: Marvell

ASIC/SOC DFT Engineer (Silicon Engineering)

will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product... and physical design Scan Design Rule Check (DRC) tools Integration and verification of Design for Test (DFT) fabrics and IP...

Lugar: USA | 27/12/2025 18:12:56 PM | Salario: S/. $130000 - 155000 per year | Empresa: SpaceX