DFT Engineer - CPU

include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, scan compression, IEEE 1500 Standard, and MBIST...

Lugar: Austin, TX | 17/12/2024 22:12:15 PM | Salario: S/. $122500 - 183700 per year | Empresa: Qualcomm

Wireless RF PHY FW Engineer

, multi-processor systems. Fluency in using lab equipment such as logic analyzers, oscilloscopes, network analyzers, spectrum...

Lugar: Sunnyvale, CA | 20/12/2024 01:12:46 AM | Salario: S/. $121900 - 183600 per year | Empresa: Apple

CPU Design Timing Engineer

of basic Static Timing Analysis fundamentals Academic understanding of circuit and logic design Key Qualifications Key...®/Tempus® Knowledge of physical design tools and methodology including logic synthesis, PnR, parasitic extraction, and logic...

Lugar: Santa Clara, CA | 13/12/2024 20:12:40 PM | Salario: S/. $121900 - 183600 per year | Empresa: Apple

Physical Design Engineer

, we will be at the center of a PHY design effort working with architecture, CAD, timing and logic design teams, with a critical impact... Architecture and HDL languages like Verilog to be able with logic design team for timing fixes Power user of industry standard...

Lugar: Cupertino, CA | 15/11/2024 22:11:38 PM | Salario: S/. $121900 - 183600 per year | Empresa: Apple

CPU Processor Power Management Verification Engineer

with architecture and RTL designers on verifying the functionality correctness of the Power Management and Clock Control logic • Develop... and execute test plans and schedules for the power management and clock control logic • Develop tests in Assembly, Scripts, System...

Lugar: Santa Clara, CA | 08/11/2024 22:11:27 PM | Salario: S/. $121900 - 183600 per year | Empresa: Apple

ASIC Design Engineer

specifications - Design, implement, and debug complex logic designs - Integrate complex IPs into the SOC - Support all front end... + 0 Years of Experience Key Qualifications Key Qualifications Experience in SoC front-end ASIC RTL digital logic...

Lugar: Cupertino, CA | 08/11/2024 21:11:47 PM | Salario: S/. $121900 - 183600 per year | Empresa: Apple

CPU DFT Verification Engineer

, and DFT designers on verifying the functionality correctness of the DFT logic • Execute test plans for DFT logic • Develop... and structural debug concepts and methodologies: JTAG, MBIST and scan Knowledge of digital logic design, debug feature, and DFT...

Lugar: Santa Clara, CA | 08/11/2024 19:11:10 PM | Salario: S/. $121900 - 183600 per year | Empresa: Apple

Graphics FE Implementation Engineer

key netlist quality milestones for your partition, engage in Lint, CDC, Logic equivalence checks and support ECO... Minimum Qualifications Relevant Coursework in Computer Architecture, Digital Logic Design and CMOS VLSI design Experience...

Lugar: Santa Clara, CA | 02/11/2024 22:11:54 PM | Salario: S/. $121900 - 183600 per year | Empresa: Apple