Layout Design Engineer

and familiarity with finFET design rules, layout dependent effects, and DFM. Tasks include creation of layout through LVS, DRC, ERC... using industry standard CAD tools such as Cadence Virtuoso Experience with closing LVS, DRC, ERC, SRAM, other PVERF checks...

Lugar: Toronto, ON - USA | 16/10/2024 21:10:23 PM | Salario: S/. No Especificado | Empresa: Untether AI

Senior Mobility Analyst

from Worldwide ERC. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need...

Lugar: San Diego, CA | 16/10/2024 17:10:27 PM | Salario: S/. $89900 - 134900 per year | Empresa: Qualcomm

Analog Layout Lead

with circuit design engineers plan/schedule work and coordinate vital layout tradeoffs as needed. Interpreting LVS, DRC and ERC... capacitance. Proficiency in interpreting physical verification reports (DRC, ERC, LVS, etc.) Experience using Cadence Virtuoso...

Lugar: Waltham, MA | 16/10/2024 17:10:56 PM | Salario: S/. No Especificado | Empresa: Apple

Analog Layout Engineer

beginning with initial floor planning and ending with fully verified, post-extracted layout (DRC, ERC, LVS, etc.). Excellent...

Lugar: Cupertino, CA | 12/10/2024 02:10:30 AM | Salario: S/. No Especificado | Empresa: Apple