Digital Design Engineer

, gain error, distortion, etc.) is an advantage. Knowledge in EDA tools such as Cadence Digital EDA suite (Genus, Tempus...

Lugar: San Diego, CA | 17/04/2026 17:04:14 PM | Salario: S/. No Especificado | Empresa: Syntiant

Physical Design Engineer

process nodes (5nm and below) Experience with Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler) automated RTL...

Lugar: Austin, TX | 16/04/2026 18:04:34 PM | Salario: S/. $15000 - 27000 per year | Empresa: Etched

CPU Synthesis CAD Engineer

nodes (5nm or lower) Strong user of synthesis tools such as Cadence Genus or Synopsys Fusion Compiler Proven track record...

Lugar: Santa Clara, CA | 11/04/2026 20:04:50 PM | Salario: S/. No Especificado | Empresa: Qualcomm

Digital Flow Enablement Solutions Architect

and running Genus/Innovus to validate techLEF correctness and library performance and DRC correctness Tempus timing flow..., Liberate MX, Liberate AMS Simulators: Spectre, AMS, Xcelium Digital: Genus, Innovus, Tempus, Voltus, PrimeTime etc The...

Lugar: USA | 28/03/2026 02:03:07 AM | Salario: S/. No Especificado | Empresa: Cadence Design Systems