Static Timing Analysis (STA) Engineer

(or Cadence Tempus) for timing analysis and Synopsys Design Compiler (or Cadence Genus) for synthesis Ability to work with large...

Lugar: Tukwila, WA | 23/06/2026 22:06:30 PM | Salario: S/. $146200 - 197800 per year | Empresa: Boeing

Lead ASIC Design Engineer

: Drive logic synthesis (e.g., Design Compiler, Genus), Static Timing Analysis (STA via PrimeTime/Tempus), and run static...

Lugar: San Jose, CA | 21/06/2026 01:06:26 AM | Salario: S/. No Especificado | Empresa: Broadcom