Senior Synthesis Engineer

Compiler/Genus), Fair knowledge in LEC, LP signoff tools Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis...

Lugar: Austin, TX | 25/06/2026 22:06:10 PM | Salario: S/. $115600 - 173400 per year | Empresa: Qualcomm

Static Timing Analysis (STA) Engineer

(or Cadence Tempus) for timing analysis and Synopsys Design Compiler (or Cadence Genus) for synthesis Ability to work with large...

Lugar: Tukwila, WA | 23/06/2026 18:06:12 PM | Salario: S/. $146200 - 197800 per year | Empresa: Boeing