Senior Engineer, Physical Design

with industry-standard EDA tools for physical design, including Cadence Genus and Innovus, and Synopsys Design Compier, IC Compiler...

Lugar: Morrisville, NC | 06/12/2025 01:12:47 AM | Salario: S/. $90400 - 133760 per year | Empresa: Marvell

Senior Engineer, Physical Design

with industry-standard EDA tools for physical design, including Cadence Genus and Innovus, and Synopsys Design Compier, IC Compiler...

Lugar: Santa Clara, CA | 05/12/2025 18:12:27 PM | Salario: S/. $89360 - 133900 per year | Empresa: Marvell

Principal/ Senior Principal Digital ASIC Circuit Design Engineer

VCS - Synthesis – Synopsys Design Compiler, Cadence Genus or Cadence RTL Compiler - Static Timing – Synopsys Primetime..., Cadence Genus or Cadence RTL Compiler - Static Timing – Synopsys Primetime or Cadence Tempus Preferred Qualifications...

Lugar: USA | 26/11/2025 18:11:45 PM | Salario: S/. $119600 - 179500 per year | Empresa: Northrop Grumman

DFT Engineer

tools (Modus and Genus) Well versed in JTAG/1500/1687 networks and BSDL, ICL and PDL knowledge Strong knowledge of logic...

Lugar: San Jose, CA | 20/11/2025 03:11:51 AM | Salario: S/. $120000 - 192000 per year | Empresa: Broadcom

DFT Engineer

tools (Modus and Genus) Well versed in JTAG/1500/1687 networks and BSDL, ICL and PDL knowledge Strong knowledge of logic...

Lugar: San Jose, CA | 19/11/2025 23:11:52 PM | Salario: S/. $120000 - 192000 per year | Empresa: Broadcom