Senior Principal Engineer, Micro-architecture and RTL
testing, and maintenance of designed blocks and reusable IPs. Produce comprehensive block uArchitecture and register Specs...
testing, and maintenance of designed blocks and reusable IPs. Produce comprehensive block uArchitecture and register Specs...
block tests on silicon during lab testing, and maintenance of designed blocks and reusable IPs. Produce comprehensive block...
is an independent function within CE responsible for validating all Marvell High-Speed PHY(Serdes/D2D) IPs, in the lab environment...
. Analyze stress and readpoint data to evaluate reliability performance across Logic, Memory, and Analog Core IPs. Review...
address subnetting o Designing and managing firewall policies, IPS/IDS, and threat controls Preferred Qualifications...
solutions (firewalls, IDS/IPS, VPNs, segmentation). Team Leadership & Development Lead by example and directly alongside...
with internally developed IPs and industry standard external IPs such as UALink, UCIe, etc. Collaborate with verification team...
) organization develops the industry’s most advanced High-Speed SerDes (HSS) IPs, covering a broad range of applications including... Lead application engineering support for high-speed SerDes IPs (NRZ and PAM4, up to 224G+) across protocols including PCIe...
) organization develops the industry’s most advanced High-Speed SerDes (HSS) IPs, covering a broad range of applications including... performance — across multi-data-rate SerDes and supporting analog IPs (analog bias, clock buffers, process monitors, temperature...
third-party EDA tools, libraries, and IPs to meet project requirements, considering performance, scalability, and cost...