Senior Staff Collateral Design and DFM Engineer

, and collaborating with cross-functional partners to develop robust mitigation rules Drive scribe line layout design and process... chip design and scribe line optimization across 3nm–16nm FinFET or sub-3nm GAA FET technologies, including Backside Power...

Lugar: Santa Clara, CA | 01/07/2026 20:07:14 PM | Salario: S/. No Especificado | Empresa: Intel