Responsible for digital design and verification of image sensor and SoC systems, including IP design, integration, analysis, and validation. Design and verify image sensor control and processing functions, as well as high-speed interfaces s...
Design, implement, maintain, and support security tools/platforms to protect company's computer systems, networks and data and assist with improving overall security posture applying knowledge in computer and information technology systems ...
Design, develop, and characterize embedded analog circuits, such as high speed I/O, SerDes, FIFO, CDR, PLL, etc. Design and debug RTL level signal synchronization, clock tree and conduct cross domain clock designs. Evaluate and characteri...
Conduct design and development of image sensor technologies, work on transistor level design of analog and mixed-signal circuits for CMOS Image Sensor such as asic_pixel array, column-amplifier, switch capacitor, comparator, ramp generator,...
Design and verify digital circuits for CMOS image sensors (CIS), including sensor array timing control logic, analog-digital interface modules, and ISP (Image Signal Processing) data pipelines, in accordance with product requirements, syste...
Primary responsibility is to bring a new product from tapeout to mass production. Candidate designs a characterization/testing plan and works with R&D teams and manufacturing engineers on technical issues, resolving these issues to meet per...
Familiar with digital design flow, including verilog RTL coding/simulation, synthesis, static timing analysis, and formality Knowledge of high performance and low power design techniques. Knowledge of FPGA and emulation platforms. Knowle...
Design and implement sensor timing control logic and contribute to ISP system-level integration Participate in chip-level architecture definition, including analog interfaces, control logic, image data processing pipelines, and power/perfo...
Lugar:
Irvine, CA | 30/05/2026 21:05:38 PM | Salario: S/. $110600 - 140000 per year | Empresa:
OmniVisionWork closely with design teams and CAD/EDA stakeholders to identify workflow bottlenecks across the chip development lifecycle-such as DRC/CDC/STA debug, regression triage, PPA convergence, and ECO iteration. This role focuses on building s...
Familiar with digital design flow, including verilog RTL coding/simulation, synthesis, static timing analysis, and formality Knowledge of high performance and low power design techniques. Knowledge of FPGA and emulation platforms. Knowle...