RF/MS IC Design Engineer, Optical Networking & SERDES

-power 5-nm 100G PAM4 DSP SoC, optimized for active electrical and optical cables Sierra: A single-chip solution for 5G Open... by developing the world’s first high-performance TV tuner chip using standard CMOS process technology. Others said we couldn’t...

Lugar: San Jose, CA | 21/11/2025 02:11:46 AM | Salario: S/. $117832 - 236090 per year | Empresa: MaxLinear

RF/MS IC Design Engineer, Optical Networking & SERDES

-power 5-nm 100G PAM4 DSP SoC, optimized for active electrical and optical cables Sierra: A single-chip solution for 5G Open... by developing the world’s first high-performance TV tuner chip using standard CMOS process technology. Others said we couldn’t...

Lugar: San Jose, CA | 19/11/2025 20:11:40 PM | Salario: S/. $117832 - 236090 per year | Empresa: MaxLinear

Associate Director, MSAT

and Process Risk Assessment (FMEA) activities to establish appropriate process control strategies (PCS). Designs, prepares... network to incorporate lessons learned from ‘sending’ sites for an optimized manufacturing process. Leads, motivates, mentors...

Lugar: Springfield, NJ | 13/12/2025 19:12:17 PM | Salario: S/. $151700 - 227600 per year | Empresa: Lantheus

Principal Engineer, Physical Design

opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance... processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, automotive, and networking applications...

Lugar: Santa Clara, CA | 28/10/2025 20:10:37 PM | Salario: S/. $146850 - 220000 per year | Empresa: Marvell

Advanced Packaging, SI/PI Principal Engineer

designs require multi-chip, multiple component configurations involving, but not limited to, 2.5D and 3D packages, Co-packaged...’s most challenging designs and integrations with industry-leading packaging technologies What You Can Expect You will be responsible...

Lugar: Burlington, VT | 26/11/2025 23:11:06 PM | Salario: S/. $148500 - 219780 per year | Empresa: Marvell

Lead Software Engineer: Front-End

and animation techniques, while ensuring that all solutions are optimized for SEO and ready for analytics integration..., and performance-optimized interfaces. Develop responsive, high-performance front-end components using JavaScript, jQuery and modern...

Lugar: Jersey City, NJ | 14/12/2025 18:12:15 PM | Salario: S/. $152000 - 215000 per year | Empresa: JPMorgan Chase

Lead Software Engineer - AIML/Python

and AI Researchers to advance experiments into more robust, scalable, highly optimized production-grade apps. Develops and writes... designs, technical credentials, and applicability for use within existing systems and information architecture. Leads...

Lugar: Jersey City, NJ | 08/12/2025 18:12:25 PM | Salario: S/. $152000 - 215000 per year | Empresa: JPMorgan Chase

RF/MS IC Design Engineer, Optical Networking & SERDES

-power 5-nm 100G PAM4 DSP SoC, optimized for active electrical and optical cables Sierra: A single-chip solution for 5G Open... by developing the world’s first high-performance TV tuner chip using standard CMOS process technology. Others said we couldn’t...

Lugar: Carlsbad, CA | 20/11/2025 23:11:29 PM | Salario: S/. $104728 - 212170 per year | Empresa: MaxLinear