RF/MS IC Design Engineer, Optical Networking & SERDES

-power 5-nm 100G PAM4 DSP SoC, optimized for active electrical and optical cables Sierra: A single-chip solution for 5G Open... by developing the world’s first high-performance TV tuner chip using standard CMOS process technology. Others said we couldn’t...

Lugar: San Jose, CA | 20/11/2025 22:11:07 PM | Salario: S/. $117832 - 236090 per year | Empresa: MaxLinear

RF/MS IC Design Engineer, Optical Networking & SERDES

-power 5-nm 100G PAM4 DSP SoC, optimized for active electrical and optical cables Sierra: A single-chip solution for 5G Open... by developing the world’s first high-performance TV tuner chip using standard CMOS process technology. Others said we couldn’t...

Lugar: San Jose, CA | 20/11/2025 03:11:16 AM | Salario: S/. $117832 - 236090 per year | Empresa: MaxLinear

Senior Mechanical/Structural Engineer, Infrastructure

to continually work towards optimized vertiport launch solutions. Responsibilities: End-to-end project ownership through hosting... networks of electrified skydecks. Apply interdisciplinary engineering skills in fields of system-level process design...

Lugar: San Carlos, CA | 01/01/2026 00:01:29 AM | Salario: S/. $134100 - 221300 per year | Empresa: Joby Aviation

Senior Mechanical/Structural Engineer, Infrastructure

to continually work towards optimized vertiport launch solutions. Responsibilities End-to-end project ownership through hosting... networks of electrified skydecks. Apply interdisciplinary engineering skills in fields of system-level process design...

Lugar: San Carlos, CA | 30/12/2025 22:12:02 PM | Salario: S/. $134100 - 221300 per year | Empresa: Joby Aviation

Advanced Packaging Technology Pathfinding and Development Engineer

and custom solutions to meet constantly evolving customer needs. Many of the new designs require multi-chip, multiple component... has partnered with the world's leading manufacturers to solve our customer’s most challenging designs and integrations with industry...

Lugar: Austin, TX | 08/01/2026 19:01:51 PM | Salario: S/. $148500 - 219780 per year | Empresa: Marvell

Advanced Packaging, SI/PI Principal Engineer

designs require multi-chip, multiple component configurations involving, but not limited to, 2.5D and 3D packages, Co-packaged...’s most challenging designs and integrations with industry-leading packaging technologies What You Can Expect You will be responsible...

Lugar: Burlington, VT | 27/11/2025 01:11:38 AM | Salario: S/. $148500 - 219780 per year | Empresa: Marvell

Lead Software Engineer-AI Platform Engineer

of architectural designs, technical credentials, and their applicability within existing systems and information architecture. Lead... that are secure, scalable, and optimized for AI and machine learning workloads. Collaborate with AI teams to understand computational...

Lugar: Jersey City, NJ | 18/01/2026 18:01:24 PM | Salario: S/. $152000 - 215000 per year | Empresa: JPMorgan Chase

Lead Software Engineer-AI Platform Engineer

of architectural designs, technical credentials, and their applicability within existing systems and information architecture. Lead... that are secure, scalable, and optimized for AI and machine learning workloads. Collaborate with AI teams to understand computational...

Lugar: Seattle, WA | 18/01/2026 18:01:25 PM | Salario: S/. $152000 - 215000 per year | Empresa: JPMorgan Chase