manufacturing processes Experience working with complex board designs PCB/FPC/RFPC (Printed Circuit Board/Flexible Printed Circuit... Experience designing for HDI flexible and rigid substrates for high volume cost optimized applications Experience in product...
Lugar:
San Jose, CA | 07/02/2026 23:02:18 PM | Salario: S/. $145000 - 245000 per year | Empresa:
Mash Gin and testing iteration to continually work towards optimized vertiport launch solutions. Responsibilities: End-to-end project... of system-level process design and initial sizing, detailed structural engineering, pressurized fluid and thermal analysis...
with the Senior Server Architect to define and maintain enterprise server architecture standards, reference designs..., and best practices for DI SW development environments Evaluate and recommend compute technologies optimized for engineering, simulation...
Lugar:
USA | 14/02/2026 00:02:17 AM | Salario: S/. $129600 - 233300 per year | Empresa:
Siemens and testing iteration to continually work towards optimized vertiport launch solutions. Responsibilities End-to-end project... of system-level process design and initial sizing, detailed structural engineering, pressurized fluid and thermal analysis...
) requiring innovative and custom solutions to meet constantly evolving customer needs. Many of the new designs require multi-chip... designs and integrations with industry-leading packaging technologies. What You Can Expect Develop packaging technology...
Lugar:
Austin, TX | 22/01/2026 22:01:44 PM | Salario: S/. $148500 - 219780 per year | Empresa:
Marvell and custom solutions to meet constantly evolving customer needs. Many of the new designs require multi-chip, multiple component... has partnered with the world's leading manufacturers to solve our customer’s most challenging designs and integrations with industry...
Lugar:
Austin, TX | 08/01/2026 18:01:27 PM | Salario: S/. $148500 - 219780 per year | Empresa:
Marvell integrity, and cost‑optimizeddesigns for high‑volume production. Review PCB layouts in collaboration with layout engineering.... Manage designs with JDM partners to provide design guidance, support build readiness and ensure production quality. Define...
Lugar:
Irvine, CA | 07/01/2026 19:01:11 PM | Salario: S/. $144800 - 214340 per year | Empresa:
Marvell-power 5-nm 100G PAM4 DSP SoC, optimized for active electrical and optical cables Sierra: A single-chip solution for 5G Open... by developing the world’s first high-performance TV tuner chip using standard CMOS process technology. Others said we couldn’t...
Lugar:
Carlsbad, CA | 07/02/2026 02:02:47 AM | Salario: S/. $104728 - 212170 per year | Empresa:
MaxLinear-power 5-nm 100G PAM4 DSP SoC, optimized for active electrical and optical cables Sierra: A single-chip solution for 5G Open... CMOS process technology. Others said we couldn’t achieve the extremely high-performance requirements using CMOS...
Lugar:
Carlsbad, CA | 05/02/2026 19:02:50 PM | Salario: S/. $104728 - 212170 per year | Empresa:
MaxLinear of customer success — solving complex problems, enabling strategic designs, and ensuring that Marvell’s cutting-edge switch... tailored training sessions for customers on Marvell’s features, architecture, and optimized implementations. Create customer...