Senior Mixed Signal IP Enablement and Debug Engineer

. HIPD creates a comprehensive portfolio of cutting-edge Mixed Signal IPs including PLLs, Serial and Parallel IO PHYs (DDR... with either serial IOs (PCIe, USB, SATA, TypeC, Ethernet) or parallel IOs (DDR, LPDDR, UCIe Die2Die) 2+ years of experience with the lab...

Lugar: Folsom, CA | 03/06/2026 02:06:23 AM | Salario: S/. No Especificado | Empresa: Intel

Senior Staff Mixed Signal IP Enablement and Debug Engineer

Sensors, PLLs, Serial and Parallel IO PHYs (DDR/LPDDR, PCIe, USB, Type-C, UCIe Die-to-Die), and Ethernet PHYs. As part... validation and debug with either serial IOs (PCIe, USB, SATA, TypeC, Ethernet) or parallel IOs (DDR, LPDDR, UCIe Die2Die) 2...

Lugar: Folsom, CA | 02/06/2026 19:06:39 PM | Salario: S/. No Especificado | Empresa: Intel