Design For Test Engineer III (IC)

using Tessent TestKompress ATPG pattern generation: Compressed and Uncompressed Mode Tools: Mentor Tessent, Cadence... Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools: VCS Mismatch...

Lugar: San Jose, CA | 05/04/2026 02:04:59 AM | Salario: S/. $95900 - 170500 per year | Empresa: Arrow Electronics

Design For Test Engineer III (IC)

using Tessent TestKompress ATPG pattern generation: Compressed and Uncompressed Mode Tools: Mentor Tessent, Cadence... Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools: VCS Mismatch...

Lugar: San Jose, CA | 02/04/2026 23:04:02 PM | Salario: S/. $95900 - 170500 per year | Empresa: Arrow Electronics

Staff DFT Engineer

of both the block level and chip top design-for-test (DFT) and automated test pattern generation (ATPG) flows for complex custom... test Execute digital logic, MBIST, and IP test pattern generation and simulation flows Analyze results and look for ways...

Lugar: Burlington, VT | 17/02/2026 19:02:39 PM | Salario: S/. $115200 - 170390 per year | Empresa: Marvell

Senior Software Engineer

, Unit of Work, Observer/Pub-Sub, Factory, Dependency Injection, Result Pattern. Proficient in Generics, Reflection...

Lugar: Dallas, TX | 18/03/2026 19:03:46 PM | Salario: S/. $92800 - 170300 per year | Empresa: PowerSchool

Senior Full Stack Developer

: Five (5)+ years working on fast paced Agile teams. Five (5)+ years of working in microservice pattern. Three (3) years...

Lugar: Virginia | 05/04/2026 20:04:25 PM | Salario: S/. $66379.5 - 170037.6 per year | Empresa: Stride