FPGA Design Engineer

using VHDL in Xilinx Vivado. Must have experience optimizing FPGA designs for resource utilization, power consumption...

Lugar: Shalimar, FL | 10/01/2025 03:01:55 AM | Salario: S/. $126100 - 227950 per year | Empresa: Leidos

Senior Opto-Mechanical Engineer

, power requirements, and mechanical interfaces of control components. Possess a Secret security clearance or higher...

Lugar: La Jolla, CA | 06/01/2025 03:01:42 AM | Salario: S/. $126100 - 227950 per year | Empresa: Leidos

Senior Opto-Mechanical Engineer

, power requirements, and mechanical interfaces of control components. Possess a Secret security clearance or higher...

Lugar: San Diego, CA | 06/01/2025 03:01:10 AM | Salario: S/. $126100 - 227950 per year | Empresa: Leidos

Senior Opto-Mechanical Engineer

, power requirements, and mechanical interfaces of control components. Possess a Secret security clearance or higher...

Lugar: El Cajon, CA | 06/01/2025 03:01:23 AM | Salario: S/. $126100 - 227950 per year | Empresa: Leidos