Lead ASIC DFT Engineer

. "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax... and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG...

Lugar: USA | 23/06/2026 17:06:06 PM | Salario: S/. No Especificado | Empresa: Vertex Elite LLC

Lead ASIC DFT Engineer

for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST..., verification, and sign-off for complex ASIC and SoC designs. Drive scan architecture, scan insertion, scan chain stitching...

Lugar: San Jose, CA | 23/06/2026 17:06:26 PM | Salario: S/. No Especificado | Empresa: Purple Hires Inc

Lead ASIC DFT Engineer

for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST..., verification, and sign-off for complex ASIC and SoC designs. Drive scan architecture, scan insertion, scan chain stitching...

Lugar: San Jose, CA | 23/06/2026 17:06:22 PM | Salario: S/. No Especificado | Empresa: Accord Technologies Inc.

ASIC Chip Design Lead

designs to closure in a fast-paced startup environment. Responsibilities Hands-on RTL Development Write, review... Hands-on experience defining and refining SDC constraints and improving post-layout timing Expertise with high-performance...

Lugar: San Jose, CA | 23/06/2026 17:06:24 PM | Salario: S/. No Especificado | Empresa: Connvertex Technologies

Lead ASIC DFT Engineer

profile consideration. "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern... for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST...

Lugar: Plano, TX | 23/06/2026 17:06:15 PM | Salario: S/. No Especificado | Empresa: Purple Hires Inc

Lead ASIC DFT Engineer

for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST..., verification, and sign-off for complex ASIC and SoC designs. Drive scan architecture, scan insertion, scan chain stitching...

Lugar: Plano, TX | 23/06/2026 17:06:08 PM | Salario: S/. No Especificado | Empresa: Purple Hires Inc

Design Engineer I

GDSII/tapeout. Develop and maintain timing constraints (SDC) for block-level and chip-level designs. Perform static... Implementation Team. This team is responsible for transforming RTL designs into manufacturable silicon, driving the implementation...

Lugar: Austin, TX | 22/06/2026 23:06:57 PM | Salario: S/. $78750 - 146250 per year | Empresa: Silicon Labs

Physical Design Engineer (PnR / PPA / Timing Closure)

. Optimize designs for Power, Performance, and Area (PPA) targets. Achieve timing closure across multiple corners and modes.... Analyze and resolve setup, hold, transition, capacitance, and noise violations. Develop and maintain timing constraints (SDC...

Lugar: Mountain View, CA | 19/06/2026 17:06:32 PM | Salario: S/. $45000 - 121000 per year | Empresa: Wipro

Lead Debug Engineer (Not for Everyone)

Description: At Steven Douglas Corp (SDC), we specialize in designing and building custom automated machines... build custom project. Machines do not cooperate on schedule, vendors miss, designs need re-work, software needs revamped...

Lugar: Painesville, OH | 12/06/2026 02:06:13 AM | Salario: S/. No Especificado | Empresa: Steven Douglas Corp

Lead ASIC DFT Engineer

Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs...-off for complex ASIC and SoC designs. Drive scan architecture, scan insertion, scan chain stitching, and scan compression...

Lugar: Houston, TX | 10/06/2026 19:06:33 PM | Salario: S/. No Especificado | Empresa: TechNeptune Consulting Inc